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Allwinner /D1H /TWI[0] /TWI_CNTR

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Interpret as TWI_CNTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (oscl)clk_count_mode 0 (a_ack)a_ack 0 (int_flag)int_flag 0 (m_stp)m_stp 0 (m_sta)m_sta 0 (ignored)bus_en 0 (low)int_en

clk_count_mode=oscl, int_en=low, bus_en=ignored

Description

TWI Control Register

Fields

clk_count_mode

0 (oscl): scl clock high period count on oscl

1 (iscl): scl clock high period count on iscl
a_ack

Assert Acknowledge
int_flag

Interrupt Flag
m_stp

Master Mode Stop
m_sta

Master Mode Start
bus_en

TWI Bus Enable

0 (ignored): undefined

1 (respond): undefined
int_en

Interrupt Enable

0 (low): The interrupt line always low

1 (high): The interrupt line will go high when INT_FLAG is set

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data